Chips including semiconductor integrated circuits undergo a variety of tests to determine whether the semiconductor devices are operating properly. For instance, scan based tests of the circuits may be performed by an automatic test equipment (ATE) configured to test one or more similarly configured chips in parallel. Scan based tests of circuits on a chip include “scan shift” and “scan capture” operations. These scan based tests can operate on a scan chain of connected registers (e.g., flip-flops or latches) that are designed for testing by inputting data and analyzing the output data from each of the scan chains.
In some cases, an ATE is configurable to input data used for testing chips at speeds from 250 MHz to 500 MHz, and in some cases even up to 1600 MHz. On the other hand, scan chains designed for test may only be able to shift in the data into the registers at much lower frequencies (e.g., ranging from 10 MHz to 100 MHz) due to chip timing and power constraints in test mode. In order to reduce scan pin requirements, bandwidth matching between the high speed scan data from the ATE and the internal scan chains may be performed by a load deserializer and an unload deserializer.
One of the problems encountered with a chip designed for testing is that a fixed bandwidth ratio limits optimization during testing. Specifically, a scan architecture of a chip may have a fixed bandwidth ratio (e.g., 4-to-1) between external scan data (from/to ATE) and internal scan chain data. Design modules located within the chip are designed to perform testing in compliance with the bandwidth ratio. However, this restricts the chip to also have a fixed bandwidth ratio, and a fixed number of scan pin requirements for all design modules in a chip. Because the external scan data rate and the internal data rate must remain fixed, a scan shift operation cannot be altered to run at desired speeds based on timing signoff, and the channel bandwidth cannot be optimized.
Another problem encountered with a chip designed for testing is that design modules are not reuse friendly. That is, a design module used in an original chip cannot be incorporated into a new chip configured with fewer available pins for testing. Further, even if the design module was incorporated into the new chip, the test patterns designed for the original chip are unusable in the new chip because of the different number of scan pins for test. In this case, for design module reuse, either additional scan pins for test must be allocated at the chip level to accommodate for different numbers of scan pins required for testing for different chips, or the design module incorporated into the new chip must be redesigned to accommodate its required number of scan pins for test. This inflexible design allows for reduction in scan pin counts and an efficient utilization of tester resources, but does not provide flexibility in cases where a design module is reused, or where a scan data bandwidth is changed.
Still another problem encountered with a chip designed for testing is that the scan data rate is fixed. Normally, the ATE channel bandwidth is fully utilized for a chip having one or more internal design modules designed for that chip. However, the ATE channel data rate or scan data rate cannot be adjusted because the internal scan chain data rate (used for loading data into the registers of the scan chain) is limited and/or fixed due to timing and power constraints.
As a previously introduced solution to the above described problems, the timing signoff of the internal scan chain shift speed can be adjusted to a higher speed. However, because this feature requires additional gate area and interconnect resources for test related paths, adjusting the internal scan chain shift speed higher is not feasible as the cost of the chip would increase. Also, if scan chains are shifted at the higher speeds, there may be a peak power issue on the ATE that needs to be addressed.